In semiconductor industry, an integrated circuit (IC) design is formed on a wafer using various fabrication processes, such as etching, deposition, implantation, annealing polishing and lithography. Especially, a lithography process transfers a pattern from a photomask to the wafer such that etching, implantation or other steps are applied only to predefined regions of the wafer. The photomask includes an IC pattern and is repeatedly used in wafer fabrication.
Usually, the photomask is patterned using an electron beam (e-beam) writing. It is more challenging to form a photomask when semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. Various new lithography processes have been approached for higher resolution such that a small feature can be precisely printed on wafers. For example, optical proximity correction (OPC) is indispensable and is used to tune the IC pattern for improved imaging effect. However, After OPC and other adjustments to the IC pattern, the modified IC pattern is more irregular with much more jogs. The e-beam writing time to mask such a photomask is much long. The mask making cycle time is prolonged and the corresponding mask making cost is higher.
Therefore, what is needed is a method and a system to provide effective IC design for the advanced IC technologies addressing the above problems and reducing the mask making cycle time.